(a) Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device and, more particularly, to a method for manufacturing a semiconductor device including the step of etching a silicon nitride film and a silicon film.
(b) Description of the Related Art
In semiconductor memory devices, such as a DRAM or flash memory, gate electrodes having a poly-metal structure are increasingly used. The poly-metal structure is such that the gate electrodes or interconnections include a polysilicon layer and an overlying metallic layer such as a tungsten (W) layer. FIG. 4 shows a conventional poly-metal structure. The gate electrode shown therein is formed on a silicon substrate via a gate insulation film 11, and includes a polysilicon film 12, a tungsten nitride (WN) film 13 and a tungsten (W) film 14 consecutively as viewed from the silicon substrate 10. The top of gate electrode is covered by a silicon nitride film and a silicon oxide film 16, which are used as a hard mask for patterning the gate electrode. The side surface of the gate electrode and hard mask is also covered by a sidewall silicon nitride film 17.
In the gate electrode structure as described above, the tungsten film having a lower resistivity is used for reducing the line resistance of the gate electrode having a smaller width. However, since the tungsten film, if formed directly on the gate insulation film, will adversely affect the transistor characteristics of the MOSFET due to the variation in the interface level in the tungsten, the polysilicon film 12 is interposed between the tungsten film 14 and the gate oxide film 11 to configure the poly-metal structure.
In addition, in the structure of FIG. 4, the tungsten nitride film 13 having a small thickness is interposed between the tungsten film 14 and the polysilicon film 12 for maintaining the film quality of the tungsten film 14 and controlling the interface resistance. Further, the sidewall oxide film 17 prevents tungsten in the tungsten film from falling to attach and contaminate the gate insulation film 11.
The gate electrode having the above poly-metal structure is manufactured by a process shown in FIGS. 5 to 8. Polysilicon film 12, tungsten nitride film 13, tungsten film 14, silicon nitride film 15 and silicon oxide film 16 are consecutively deposited on a gate insulation (oxide) film 11, followed by patterning the silicon nitride film 15 and silicon oxide film 16 to form a hard mask by using a photoresist mask.
After removing the photoresist mask, or while leaving the photoresist mask as it is, the tungsten film 14 is patterned using the hard mask 15, 16 as an etching mask. This patterning step is stopped after slightly etching a top portion of the polysilicon film 12 to leave a non-etched portion of the polysilicon film 12, as shown in FIG. 5.
Thereafter, a thin silicon nitride film 17a is deposited on the entire surface, as shown in FIG. 6. The silicon nitride film 17a is then etched using an anisotropic etching technique to leave the sidewall silicon nitride film 17 on the side surface of the gate electrode structure, as shown in FIG. 7. The remaining polysilicon film 12 exposed from the sidewall silicon nitride film 17 is then etched using an anisotropic etching technique to obtain the gate electrode structure as shown in FIG. 8.
The etching of the silicon nitride film 17a and polysilicon layer 12 is conducted in a single chamber, although different etching conditions are used therefor. For example, after the etching of the silicon nitride film 17a is finished, the plasma discharge is stopped in the chamber, and again started using a different recipe to etch the polysilicon film 12 in the same chamber. Such an anisotropic etching process using the plasma etching system is described in Patent Publication JP-1997-64017A, for example.
In general, the etching treatment generates reaction products, which gradually accumulate in the etching chamber during the etching treatment for a plurality of wafers. For the case of etching the gate polysilicon film, reaction products include silicon (Si) compounds. FIG. 1 shows the situation of the reaction products accumulated in the etching chamber. It is shown that the reaction products 26 are attached on the wall and ceiling of the etching chamber 21 in FIG. 1. The reaction products thus accumulated cause problems as detailed hereinafter.
First, the process condition varies due to the accumulated reaction products. More specifically, the proceeding of the etching treatment gradually changes the atmosphere within the chamber 21, whereby the thickness or shape of the film formed by the etching treatment changes within a lot or between lots. For example, the accumulation of the reaction products in the chamber increases the line with of the interconnections patterned on the wafer, and changes the side surface of the interconnections from a vertical plane to an inclined plane.
Second, particles fall from the accumulated reaction products. More specifically, an excessive amount of reaction products, if accumulated on the wall or ceiling of the chamber, causes particles to fall from the reaction products onto the wafer now subjected to the etching treatment and to contaminate the atmosphere of the chamber. For avoiding the fall of the particles, dry cleaning of the etching chamber is generally performed. The dry cleaning of the etching chamber uses a specific condition different from the condition of the anisotropic etching, the specific condition using plasma discharge suited to removing the reaction products.
Techniques for the dry cleaning include a first technique using a dummy wafer in the dry cleaning for each lot of target wafers to be etched, and a second technique using wafer-less dry cleaning for each target wafer to be etched. The first technique is shown in the flowchart of FIG. 9. In this example, wafers of a single lot to be etched includes 25 wafers, and a dummy wafer is used in the dry cleaning (step S21) before etching wafers of the lot in step S22. In the first technique, since an electrode 22 (FIG. 1) on which the target wafer is to be mounted is covered by the dummy wafer during the dry etching, the electrode 22 is not damaged after the dry cleaning is performed even for a relatively long time. The first technique, however, has a disadvantage in that use of the dummy wafer raises the total cost for the etching treatment. In addition, since the wafers in the lot are sequentially subjected to the etching treatment, a wafer appearing in the finial stage of the lot is more liable to the fall of the reaction products than another wafer appearing in the initial stage of the lot, due to the undesirable variation in the process condition within the chamber.
The second technique is shown in the flowchart of FIG. 10, wherein the wafer-less dry cleaning in step S31 is conducted before every etching treatment in step S32 for the target wafer. The wafer-less cleaning is also referred to as in-situ cleaning. The second technique removes the reaction products generated in the etching treatment for a single target wafer, before performing a subsequent etching step. This technique reduces the cost for the dummy wafer and suppresses the variation in the process condition.
The main stream of the current cleaning technique is directed to the wafer-less cleaning. The wafer-less cleaning, however, has disadvantages as detailed below. First, the electrode is damaged in the wafer-less cleaning because the electrode is directly exposed to the plasma, to thereby have a shorter lifetime. The damages on the electrode include etching of the electrode itself, which causes flaw or crack on the surface and degradation of flatness on the surface. These damages may reduce the electrostatic absorption power of the electrode and obstacle transfer of the wafers due to the misalignment of the wafers with respect to the electrode and thus a carriage for the wafers.
Second, the electrode causes metallic contamination. The electrode is generally made of ceramic, which includes therein heavy metals such as Ti and Zn in an amount depending on the manufacturer. The dry cleaning scatters the heavy metals, which attach onto the wall or ceiling of the etching chamber, and fall onto the product wafers thereby causing contamination of the final products. The metallic contamination should be avoided especially in the case of plasma etching of the gate polysilicon film, because the gate oxide film is exposed during the etching and the metallic atoms degrade the transistor characteristics if attached onto the gate oxide film.